The present invention generally relates to a device and a method for monitoring an operating frequency of a system clock signal, and more specifically, to a device and a method for monitoring a pulse width of each logic pulse of a system clock duty cycle.
The basic components of a computer are a system clock, a central processing unit, an input-output unit, a memory unit and a bus structure. The system clock generates a system clock signal that is received by the various units of the computer. In response to the system clock signal, the units of the computer input information from the bus structure as well as output information to the bus structure. This information is representative of either data, an instruction, or an address. Therefore, it is essential that the integrity of the information is maintained at all times.
A system clock signal that is generated at a non-operable frequency, i.e. any frequency that is faster than the longest reactive delay of any unit of the computer, causes internal timing problems that will effect the integrity of the information. Conversely, a system clock signal that is generated at an operating frequency, i.e. any frequency that is slower than the longest reactive delay of any unit of the computer, does not cause any internal timing problems that will effect the integrity of the information. Consequently, the system clock is typically intended to generate the system clock signal at an operating frequency that yields high performance for the computer.
Unfortunately, the system clock signal may be vulnerable to manipulation by an outside source. This manipulation involves decreasing the system clock signal to or below an operating frequency that enables data to be extracted from the computer. Such data extraction is not desirable when the information represents a trade secret, a confidential business plan, a classified military strategy, a private financial portfolio, or the like. In addition, manipulation of the system clock signal may yield unpredictable results during digital communications (modem), frequency modulations, phase modulations and frequency syntheses, especially if the system clock signal is inputted into a phase-locked loop. Such unpredictable results effect the integrity of the information.
For each computer, there exists a minimum operating frequency for the system clock signal that will ensure that data cannot be extracted from computer and that unpredictable results do not occur within the computer. What is therefore needed is a device and a method that can monitor the system clock signal in order to detect when the signal clock signal is being generated at an operating frequency that is equal to or slower than the minimum operating frequency for the system clock signal. What is also needed is a device and a method that can monitor the system clock signal in order to detect when the system clock signal is at risk of being generated at an operating frequency that is equal to or slower than the minimum operating frequency for the system clock signal.